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January 2001 Advance Information
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AS7C1024A AS7C31024A
5V/3.3V 128KX8 CMOS SRAM (Evolutionary Pinout)
Features
* AS7C1024A (5V version) * AS7C31024A (3.3V version) * Industrial and commercial temperatures * Organization: 131,012 words x 8 bits * High speed
- 10/12/15/20 ns address access time - 3/3/4/5 ns output enable access time
* Latest 6T 0.25u CMOS technology * 2.0V data retention * Easy memory expansion with CE1, CE2, OE inputs * TTL/LVTTL-compatible, three-state I/O * 32-pin JEDEC standard packages
- 300 mil SOJ - 400 mil SOJ - 8 x 20mm TSOP I
* Low power consumption: ACTIVE
- 660 mW (AS7C1024A) / max @ 10 ns - 324 mW (AS7C31024A) / max @ 10 ns
* ESD protection 2000 volts * Latch-up current 200 mA
* Low power consumption: STANDBY
- 55 mW (AS7C1024A) / max CMOS - 36 mW (AS7C31024A) / max CMOS
Logic block diagram
VCC GND Input buffer A0 A1 A2 A3 A4 A5 A6 A7 A8 I/O7 512x256x8 Array (1,048,576) Sense amp
Pin arrangement
32-pin TSOP I (8 x 20mm) A11 A9 A8 A13 WE CE2 A15 VCC NC A16 A14 A12 A7 A6 A5 A4 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 OE A10 CE1 I/O7 I/O6 I/O5 I/O4 I/O3 GND I/O2 I/O1 I/O0 A0 A1 A2 A3 NC A16 A14 A12 A7 A6 A5 A4 A3 A2 A1 A0 I/O0 I/O1 I/O2 GND 32-pin SOJ (300 mil) 32-pin SOJ (400 mil) 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 VCC A15 CE2 WE A13 A8 A9 A11 OE A10 CE1 I/O7 I/O6 I/O5 I/O4 I/O3
AS7C1024A AS7C31024A
Row decoder
I/O0 Column decoder A9 A10 A11 A12 A13 A14 A15 A16 WE OE CE1 CE2
Control circuit
Selection guide
AS7C1024A-10 AS7C31024A-10
AS7C1024A-12 AS7C31024A-12 12 3 110 80 10 10
AS7C1024A-15 AS7C31024A-15 15 4 100 80 10 10
AS7C1024A-20 AS7C31024A-20 20 5 100 80 15 15
AS7C1024A AS7C31024A
Unit ns ns mA mA mA mA
Maximum address access time Maximum output enable access time Maximum operating current Maximum CMOS standby current ASAS7C1024A AS7C31024A AS7C1024A AS7C31024A
10 3 120 90 10 10
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Copyright (c) Alliance Semiconductor. All rights reserved.
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AS7C1024A AS7C31024A
Functional description
The AS7C1024A and AS7C31024A are high performance CMOS 1,048,576-bit Static Random Access Memory (SRAM) devices organized as 131,012 words x 8 bits. It is designed for memory applications where fast data access, low power, and simple interfacing are desired. Equal address access and cycle times (tAA, tRC, tWC) of 10/12/15/20 ns with output enable access times (tOE) of 3/3/4/5 ns are ideal for high performance applications. Active high and low chip enables (CE1, CE2) permit easy memory expansion with multiple-bank systems. When CE1 is high or CE2 is low the devices enter standby mode. If inputs are still toggling, the device will consume ISB power. If the bus is static, then full standby power is reached (ISB1). For example, the AS7C31024A is guaranteed not to exceed 36mW under nominal full standby conditions. All devices in this family will retain data when VCC is reduced as low as 2.0V. A write cycle is accomplished by asserting write enable (WE) and both chip enables (CE1, CE2). Data on the input pins I/O0-I/O7 is written on the rising edge of WE (write cycle 1) or the active-to-inactive edge of CE1 or CE2 (write cycle 2). To avoid bus contention, external devices should drive I/O pins only after outputs have been disabled with output enable (OE) or write enable (WE). A read cycle is accomplished by asserting output enable (OE) and both chip enables (CE1, CE2), with write enable (WE) high. The chips drive I/O pins with the data word referenced by the input address. When either chip enable is inactive, output enable is inactive, or write enable is active, output drivers stay in high-impedance mode.
Absolute maximum ratings
Parameter Voltage on VCC relative to GND Voltage on any pin relative to GND Power dissipation Storage temperature (plastic) Ambient temperature with VCC applied DC current into outputs (low) AS7C1024A AS7C31024A Both Both Both Both Both Symbol Vt1 Vt1 Vt2 PD Tstg Tbias IOUT Min -0.50 -0.50 -0.50 - -65 -55 - Max +7.0 +5.0 VCC +0.50 1.0 +150 +125 20 Unit V V V W C C mA
Note: Stresses greater than those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions outside those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.
Truth table
CE1 H X L L L CE2 X L H H H WE X X H H L OE X X H L X Data High Z High Z High Z DOUT DIN Mode Standby (ISB, ISB1) Standby (ISB, ISB1) Output disable (ICC) Read (ICC) Write (ICC)
Key: X = Don't Care, L = Low, H = High
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Recommended operating conditions
Parameter Supply voltage Device AS7C1024A AS7C31024A ASAS7C1024A Input voltage AS7C31024A commercial industrial Symbol VCC VCC VIH VIH VIL Ambient operating temperature
Min 4.5 3.0 2.2 2.0 -0.5 0 -40
Nominal 5.0 3.3 - - - - -
Max 5.5 3.6 VCC + 0.5 VCC + 0.5 0.8 70 85
Unit V V V V V C C
TA TA
VILmin. = -3.0V for pulse width less than tRC/2.
DC operating characteristics (over the operating range)1
-10 Parameter Input leakage current Output leakage current Operating power supply current Sym |ILI| |ILO| Test conditions VCC = Max, VIN = GND to VCC VCC = Max, CE1 = VIH or CE2 = VIL, VOUT = GND to VCC VCC = Max, CE1 = VIL, CE2 = VIH, f = fMax, IOUT = 0 mA VCC = Max, CE1 VIH and/or CE2 VIL, VIN = VIH or VIL, f = fMax, IOUT = 0mA VCC = Max, CE1 VCC-0.2V VIN GND + 0.2V or VIN VCC -0.2V, f = 0 IOL = 8 mA, VCC = Min IOH = -4 mA, VCC = Min VCC = 2.0V CE1 VCC-0.2V or CE2 0.2V VIN VCC-0.2V or VIN 0.2V AS7C1024A AS7C31024A Device Both Both AS7C1024A AS7C31024A AS7C1024A AS7C31024A AS7C1024A AS7C31024A -12 -15 -20 Unit Min Max Min Max Min Max Min Max - - - - - - - - - 2.4 1 1 120 90 30 30 10 10 0.4 - 1 1 - - - - - - - - - 2.4 1 1 110 80 25 25 10 10 0.4 - 1 1 - - - - - - - - - 2.4 1 1 100 80 20 20 10 10 0.4 - 1 1 - - - - - - - - - 2.4 1 1 100 mA 80 20 mA 20 15 mA 15 0.4 - 5 5 V V mA mA A A
ICC
ISB Standby power supply current ISB1 VOL VOH
Output voltage
Data retention current
ICCDR
Capacitance (f = 1 MHz, Ta = 25 C, VCC = NOMINAL)2
Parameter Input capacitance I/O capacitance Symbol CIN CI/O Signals A, CE1, CE2, WE, OE I/O Test conditions VIN = 0V VIN = VOUT = 0V Max 5 7 Unit pF pF
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AS7C1024A AS7C31024A
Read cycle (over the operating range)3,9,12
-10 Parameter Read cycle time Address access time Chip enable (CE1) access time Chip enable (CE2) access time Output enable (OE) access time Output hold from address change CE1 Low to output in low Z CE2 High to output in low Z CE1 Low to output in high Z CE2 Low to output in high Z OE Low to output in low Z OE High to output in high Z Power up time Power down time Symbol tRC tAA tACE1 tACE2 tOE tOH tCLZ1 tCLZ2 tCHZ1 tCHZ2 tOLZ tOHZ tPU tPD Min 10 - - - - 2 0 0 - - 0 - 0 - Max - 10 10 10 3 - - - 3 3 - 3 - 10 12 - - - - 3 0 0 - - 0 - 0 - -12 Min Max - 12 12 12 3 - - - 3 3 - 3 - 12 15 - - - - 3 0 0 - - 0 - 0 - -15 Min Max - 15 15 15 4 - - - 4 4 - 4 - 15 20 - - - - 3 0 0 - - 0 - 0 - -20 Min Max - 20 20 20 5 - - - 5 5 - 5 - 20 Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns 5 4, 5, 12 4, 5, 12 4, 5, 12 4, 5, 12 4, 5 4, 5 4, 5, 12 4, 5, 12 3 3, 12 3, 12 Notes
Key to switching waveforms
Rising input Falling input Undefined / don't care
Read waveform 1 (address controlled)3,6,7,9,12
tRC Address tAA DOUT Data valid tOH
Read waveform 2 (CE1, CE2, and OE controlled)3,6,8,9,12
CE1 CE2 OE DOUT Current supply tACE1, tACE2 tCLZ1, tCLZ2 tPU Data valid tPD 50% 50% ICC ISB tOE tOLZ tOHZ tCHZ1, tCHZ2 tRC1
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Write cycle (over the operating range)11, 12
-10 Parameter Write cycle time Chip enable (CE1) to write end Chip enable (CE2) to write end Address setup to write end Address setup time Write pulse width Address hold from end of write Data valid to write end Data hold time Write enable to output in high Z Output active from write end Symbol tWC tCW1 tCW2 tAW tAS tWP tAH tDW tDH tWZ tOW Min 10 8 8 8 0 7 0 5 0 - 1 Max - - - - - - - - - 6 - 12 10 10 9 0 8 0 6 0 - 1 -12 Min Max - - - - - - - - - 6 - 15 12 12 10 0 9 0 8 0 - 1 -15 Min Max - - - - - - - - - 6 - 20 12 12 12 0 12 0 10 0 - 2 -20 Min Max - - - - - - - - - 8 - Unit ns ns ns ns ns ns ns ns ns ns ns 4, 5 4, 5 4, 5 12 12 12 Notes
Write waveform 1 (WE controlled)10,11,12
tWC tAW Address tWP WE tAS DIN tWZ DOUT tDW Data valid tOW tDH tAH
Write waveform 2 (CE1 and CE2 controlled)10,11,12
tWC tAW Address tAS CE1 CE2 tWP WE tWZ DIN DOUT tDW Data valid tDH tCW1, tCW2 tAH
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AS7C1024A AS7C31024A
Data retention characteristics (over the operating range)
Parameter VCC for data retention Chip deselect to data retention time Operation recovery time Input leakage current Symbol VDR tCDR tR | ILI | Test conditions VCC = 2.0V CE1 VCC-0.2V or CE2 0.2V VIN VCC-0.2V or VIN 0.2V Device Min 2.0 0 tRC - Max - - - 1 Unit V ns ns A
Data retention waveform
Data retention mode VCC VCC tCDR CE1 VIH VDR VIH VDR 2.0V VCC tR
AC test conditions
- - - - Output load: see Figure B or Figure C. Input pulse level: GND to 3.0V. See Figure A. Input rise and fall times: 2 ns. See Figure A. Input and output timing reference levels: 1.5V.
Thevenin equivalent: 168W DOUT +1.728V (5V and 3.3V) +5V 480W +3.0V GND 90% 10% 2 ns 90% 10% DOUT 255W C(14) DOUT 255W +3.3V 320W C(14)
Figure A: Input pulse
GND Figure B: 5V Output load
GND Figure C: 3.3V Output load
Notes
1 2 3 4 5 6 7 8 9 10 11 12 13 During VCC power-up, a pull-up resistor to VCC on CE1 is required to meet ISB specification. This parameter is sampled and not 100% tested. For test conditions, see AC Test Conditions, Figures A, B, and C. tCLZ and tCHZ are specified with CL = 5pF, as in Figure C. Transition is measured 500mV from steady-state voltage. This parameter is guaranteed, but not 100% tested. WE is High for read cycle. CE1 and OE are Low and CE2 is High for read cycle. Address valid prior to or coincident with CE1 transition Low. All read cycle timings are referenced from the last valid address to the first transitioning address. CE1 or WE must be High or CE2 Low during address transitions. Either CE1 or WE asserting high terminates a write cycle. All write cycle timings are referenced from the last valid address to the first transitioning address. CE1 and CE2 have identical timing. C=30pF, except all high Z and low Z parameters, C=5pF.
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Package dimensions
32-pin SOJ 300 mil Min Max 0.145 0.025 0.086 0.105 0.026 0.032 0.014 0.020 0.006 0.013 0.820 0.830 0.250 0.275 0.292 0.305 0.330 0.340 0.050 BSC 32-pin SOJ 400 mil Min Max 0.145 0.025 0.086 0.115 0.026 0.032 0.015 0.020 0.007 0.013 0.820 0.830 0.360 0.380 0.395 0.405 0.435 0.445 0.050 BSC
D e E1 E2
Pin 1 c A2 E A1
B A b Seating Plane
A A1 A2 B b c D E E1 E2 e
a;lsdfj;alksdfj;alkfdsa;lsdfj;alksdfj;alkfdsa;lsdfj;alks dfj;alkfdsa;lsdfj;alksdfj;alkfdsa;lsdfj;alksdfj;alkfdsa ;lsdfj;alksdfj;alkfdsa;lsdfj;alksdfj;alkfdsa;lsdfj;alksd fj;alkfdsa;lsdfj;alksdfj;alkfds
b
e c D Hd L A2 A A1
pin 1
pin 32
A A1 A2 b c D e E Hd L
32-pin TSOP 8x20 mm Min Max - 1.20 0.05 0.15 0.95 1.05 0.17 0.27 0.10 0.21 18.20 18.60 0.50 nominal 7.80 8.20 19.80 20.20 0.50 0.70 0 5
E
pin 16
pin 17
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ASAS7C1024A ASAS7C31024A
Ordering codes
Package \ Access time
Volt/Temp 5V commercial 5V industrial 3.3V commercial 3.3V industrial 5V commercial 5V industrial 3.3V commercial 3.3V industrial 5V commercial 5V industrial 3.3V commercial 3.3V industrial
10 ns AS7C1024A-10TJC AS7C1024A-10TJI
12 ns AS7C1024A-12TJC AS7C1024A-12TJI
15 ns AS7C1024A-15TJC AS7C1024A-15TJI AS7C31024A-15TJC AS7C31024A-15TJI AS7C1024A-15JC AS7C1024A-15JI AS7C31024A-15JC AS7C31024A-15JI AS7C1024A-15TC AS7C1024A-15TI AS7C31024A-15TC AS7C31024A-15TI
20 ns AS7C1024A-20TJC AS7C1024A-20TJI AS7C31024A-20TJC AS7C31024A-20TJI AS7C1024A-20JC AS7C1024A-20JI AS7C31024A-20JC AS7C31024A-20JI AS7C1024A-20TC AS7C1024A-20TI AS7C31024A-20TC AS7C31024A-20TI
Plastic SOJ, 300 mL
AS7C31024A-10TJC AS7C31024A-12TJC AS7C31024A-10TJI AS7C1024A-10JC AS7C1024A-10JI AS7C31024A-10JC AS7C31024A-10JI AS7C1024A-10TC AS7C1024A-10TI AS7C31024A-10TC AS7C31024A-10TI AS7C31024A-12TJI AS7C1024A-12JC AS7C1024A-12JI AS7C31024A-12JC AS7C31024A-12JI AS7C1024A-12TC AS7C1024A-12TI AS7C31024A-12TC AS7C31024A-12TI
Plastic SOJ, 400 mL
TSOP 8x20
Part numbering system
AS7C SRAM prefix X Blank=5V CMOS 3=3.3V CMOS 1024 Device number -XX Access time X Package:T=TSOP 8x20 J=SOJ 400 mil TJ=SOJ 300 mil X Temperature range C = Commercial, 0C to 70C I = Industrial, -40C to 85C
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(c) Copyright Alliance Semiconductor Corporation. All rights reserved. Our three-point logo, our name and Intelliwatt are trademarks or registered trademarks of Alliance. All other brand and product names may be the trademarks of their respective companies. Alliance reserves the right to make changes to this document and its products at any time without notice. Alliance assumes no responsibility for any errors that may appear in this document. The data contained herein represents Alliance's best data and/or estimates at the time of issuance. Alliance reserves the right to change or correct this data at any time, without notice. If the product described herein is under development, significant changes to these specifications are possible. The information in this product data sheet is intended to be general descriptive information for potential customers and users, and is not intended to operate as, or provide, any guarantee or warrantee to any user or customer. Alliance does not assume any responsibility or liability arising out of the application or use of any product described herein, and disclaims any express or implied warranties related to the sale and/or use of Alliance products including liability or warranties related to fitness for a particular purpose, merchantability, or infringement of any intellectual property rights, except as express agreed to in Alliance's Terms and Conditions of Sale (which are available from Alliance). All sales of Alliance products are made exclusively according to Alliance's Terms and Conditions of Sale. The purchase of products from Alliance does not convey a license under any patent rights, copyrights, mask works rights, trademarks, or any other intellectual property rights of Alliance or third parties. Alliance does not authorize its products for use as critical components in life-supporting systems where a malfunction or failure may reasonably be expected to result in significant injury to the user, and the inclusion of Alliance products in such life-supporting systems implies that the manufacturer assumes all risk of such use and agrees to indemnify Alliance against all claims arising from such use.

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